The present invention relates to a semiconductor memory and, more particularly, to a semiconductor memory that can latch output data.
Generally, in a memory such as a ROM or a RAM incorporated into a logic LSI, a latch circuit is provided for each of the bit lines, in order to prevent erroneous data from being read out from the memory cells to a peripheral circuit. More specifically, the latch circuit latches the potential of the bit line at a prescribed timing, and outputs the latched potential to the peripheral circuit.
In a synchronous ROM, for example, the potentials of all bit lines are precharged to a positive value during the high or H level half cycle of a clock signal by a precharge circuit. Also, during the H level half cycle of the clock signal, a row decoder decodes an address code. When the clock signal falls from an H level to a low or L level, the positive potential is applied by the row decoder to a selected word line. A transistor coupled at the intersection of the selected word line and any bit line discharges this bit line, whereby the potential of the bit line falls to the L level. The potentials of the other bit lines remain at the H level, i.e., the precharge level. The latch circuits provided for each of the bit lines are switched from a latch mode to a through mode when the potential of every bit line is set to the H level or the L level. Therefore, only the potential of each bit line thus established is output to the peripheral circuit. The potential of any bit line, which is changing from the H level to the L level as the bit line is discharged by the transistor, i.e., an erroneous data, is not output to the peripheral circuit.
The operation mode of each latch circuit is also controlled by the clock signal. Usually, a delay circuit outputs a control signal upon the lapse of a predetermined period after the clock signal falls from the H level to the L level. This control signal switches the operation mode of the latch circuit from the latch mode to the through mode.
Hence, if the delay time set in the delay circuit is appropriate, the potential of any bit line can be output at the time the potential is set to the H level or the L level. In this case, correct data can be read from the memory at high speed. However, it is extremely difficult to set a proper delay time in the delay circuit. The period between the time the clock signal falls from the H level to the L level and the time the potential of the bit line is set is the sum of the period required for the potential of the word line to rise to a predetermined value and the discharge period of the bit line. The discharge period is determined by the inherent capacitance of the bit line and also by the diffusion capacitance of the transistor coupled to this bit line. In particular, it is difficult to correctly calculate the proper delay time for the recently-developed LSI memory having a multi-layer wiring structure, since many conductive layers cross each bit line, and it is difficult to determine the individual capacitances between the bit line, on the one hand, and each of these layers, on the other.
When the delay time set in the delay circuit is too short, the latch circuit is switched to the through mode before the potential of the bit line is established. In this case, the memory reads out erroneous data, causing errors in the peripheral circuit, or resulting in an increase in the power consumption of the latch circuit. Conversely, when the delay time set in the delay circuit is sufficiently long to prevent the reading of erroneous data, the access time of the memory is lengthened, in which case, the operation speed of the peripheral circuit is inevitably reduced.